Bsnes WIP

[Robert]

Source: http://byuu.cinnamonpirate.com/?page=bsnes...=3&browser=

 

10/24/2006 - WIP update

Wrote a scheduler for bsnes which gains an extra ~8-16% speedup, depending on how much communication occurs between the S-CPU and S-SMP. This new scheduler basically allows either the S-CPU or S-SMP to run an entire frames' worth of opcodes before synchronizing if possible, whereas before there was a force sync after every opcode. The scheduler is also now completely responsible for interfacing with libco, so all cothreading is handled here. Now, for instance, synchronization between the S-CPU and S-SMP involves a direct thread switch from the S-CPU thread to the S-SMP thread, whereas before this would require a switch from S-CPU to the main execution thread, and then to the S-SMP thread. Lastly, it also optimizes one more edge case. If one processor tries reading from or writing to another processor, but the processor performing this read/write request is currently behind execution of the other processor, then no synchronization is necessary. bsnes can now execute the theoretical limit of CPU/SMP opcodes in a row with absolutely zero accuracy loss. I doubt I will be able to gain any more speed out of libco. It has now increased speed in totality from the old cycle-based cores by over 40%. One last great thing about the new scheduler is that it also will allow multiple clocks of varying frequencies to be run at the same time. Meaning, even though I've no interest in adding either at this time, a CPUSA1 or CPUSFX sync clock would now be far easier to implement. I also optimized the CPUSMP clock to perform a 32*32=64bit multiplication, thanks to TRAC pointing out my casting mistake which was performing a far more costly 32*64=64bit multiplication when not necessary.

Next up, the S-DSP is now enslaved inside the S-SMP, meaning S-DSP SPCRAM accesses will no longer desynchronize with the S-SMP for up to one opcode as in bsnes v0.017-v0.018.

Lastly, some fixes to the S-SMP opcode core. Added support for reads that occur during most of the mov instructions, and corrected cmpw to take four cycles instead of five like addw and subw. I also adjusted the S-DSP to run at 32040hz, and moved PAL S-CPU's speed back to 21281370hz, which is more in line of what has been observed in the past. NTSC S-CPU remains unchanged at 21477272hz. Earthworm Jim 2 sound effects still work in all regions.